1. Field of the Invention
The present invention relates to a shift register and a flat panel display device including the same.
2. Discussion of the Related Art
With the advance of multimedia, display devices are increasing in importance. Therefore, flat panel display (FPD) devices, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), organic light emitting display devices, etc., are being commercialized. Among such FPD devices, LCD devices and organic light emitting display devices have excellent characteristics such as thinness, light weight, and low power consumption. Thus, they are widely used as display devices for notebook computers, televisions, tablet computers, monitors, smart phones, portable display devices, portable information devices, etc.
The LCD devices and the organic light emitting display devices include a display panel that includes a plurality of pixels including a thin film transistor (TFT) connected to a data line and a gate line, a data driver that supplies respective data voltages to a plurality of the data lines, and a gate driver that is configured with a shift register for sequentially supplying a gate signal to a plurality of the gate lines.
Generally, each of the data driver and the gate driver is implemented as an integrated circuit (IC). Such a data driving IC and gate driving IC are mounted on a flexible circuit film such as a tape carrier package (TCP) or a chip-on film (COF), and adhered to a display panel.
Display devices, having a gate-in panel (GIP) structure in which the shift register configuring the gate driver is built into the display panel when a process of manufacturing the TFTs of the respective pixels is being performed, are being developed to reduce the number of circuit elements, the manufacturing cost, and a bezel width.
FIG. 1 is a diagram describing a related art shift register built in a display panel of a display device having the GIP structure.
Referring to FIG. 1, the related art shift register includes n number of stages ST1 to STn which are selectively connected to first and second clock signal supply lines through first and second clock signals CLK1 and CLK2 respectively supplied, and are driven in cascade according to a gate start signal Vst.
The gate start signal Vst is supplied to the first stage ST1. Also, each of the second to nth stages ST2 to STn receives an output signal of a stage (for example, one of the stages ST1 to STn-1) previous thereto as the gate start signal Vst.
Each of the n stages ST1 to STn includes: a pull-up transistor that is turned on according to a voltage of a first node, and receives only one of the first and second clock signals CLK1 and CLK2 to supply the received clock signal to a corresponding gate line GL as a gate-on voltage pulse; a pull-down transistor that is turned on according to a voltage of a second node, and supplies a gate-off voltage Voff to the gate line GL; and a node controller that is configured with a plurality of node control transistors, and controls the voltage of each of the first and second nodes. Each of the n stages ST1 to STn supplies a gate-on voltage pulse of a gate-on voltage corresponding to the first or second clock signal CLK1 or CLK2 to a corresponding gate line GL through the pull-up transistor which is turned on with the voltage of the first node controlled by the node controller according to the gate start signal Vst, and then supplies the gate-off voltage Voff to the corresponding gate line GL through the pull-down transistor which is turned on with the voltage of the second node controlled by the node controller.
In the above-described shift register, the pull-up transistor is formed to have an area relatively greater than other transistors, for stably supplying the gate-on voltage pulse to the gate line corresponding thereto. For this reason, an area of each stage is enlarged.
In addition, in the display device including the built-in gate driver configured with the shift register, since one stage is needed for driving one gate line, an area occupied by the gate driver is enlarged, causing an increase in bezel width.